1. Field of the Invention
The present invention relates to a semiconductor device of silicon-on-insulator (SOI) structure comprising an insulation layer having a silicon layer provided thereon. Particularly, the present invention relates to a semiconductor device of an SOI structure having a gettering site.
2. Description of Related Art
During a process of manufacturing a semiconductor device, contaminants [for example, a metal contaminant; copper (Cu), iron (Fe), or nickel (Ni)] are sometimes introduced into a substrate at the time of fabrication of a semiconductor element or formation of contact holes. In the event that such contaminants are introduced into the substrate, the contaminants diffuse into element fabrication regions on the substrate through heat treatment in a subsequent stage. The contaminants disadvantageously deteriorate the characteristics of semiconductor elements fabricated in the respective element fabrication regions. For example, if a MOS transistor is fabricated on the substrate, the withstand voltage of a gate insulation film of the MOS transistor will be disadvantageously deteriorated. If a P/N-type impurity junction section is formed, a leakage current developing in the P/N-type impurity junction will be disadvantageously increased.
In the case of a semiconductor device employing a conventional bulk semiconductor substrate on which semiconductor elements are formed, gettering sites are formed on the reverse surface of the semiconductor substrate or the bulk semiconductor substrate, in order to prevent deterioration of characteristics of the semiconductor element, which would otherwise be caused by the contaminants. Gettering represents a technique of forming gettering sites, such as crystal defects, and fixedly capturing contaminants.
In a semiconductor device field today, from the view points of achieving higher-density configuration and higher-speed operation, attention is being given to an SOI substrate of SOI structure comprising a support substrate coated with a insulation layer and a silicon layer formed on the insulation layer, in lieu of a conventional bulk semiconductor substrate. In the case of the SOI substrate, even if gettering sites are formed on a support substrate corresponding to the conventional bulk semiconductor substrate, in order to cause the gettering sites to capture contaminants included in a silicon layer, the contaminants must pass through a insulation layer interposed between the silicon layer and the support substrates. Contaminants which do not have sufficient kinetic energy to pass through the insulation layer cannot be captured by the gettering sites. For this reason, the gettering technique becomes less effective for recently developed LSI manufacturing processes for forming an LSI circuit at a comparatively low temperature.
Japanese Patent Laid-Open Nos. Hei-4-72631 and 8-191140 describe a technique for forming gettering sites on the entire bottom surface of a silicon layer constituting an SOI substrate (hereinafter referred to as the "first gettering technique"). Further, Japanese Patent Laid-Open No. Hei-8-45943 describes a technique for gettering contaminants through use of a technique of forming a polycrystalline silicon layer, serving as a gettering site, so as to cover an element isolation region (hereinafter referred to as the "second gettering technique").
According to the first conventional gettering technique, gettering sites are formed on a silicon layer. In a case where an LSI circuit comprising a silicon layer having a thickness of 200 nm or less is manufactured, a leakage current develops across electronic elements fabricated on the surface of the silicon layer, thereby disadvantageously deteriorating the characteristics of a semiconductor device.
Further, the second conventional gettering technique overcomes a drawback of the first gettering technique but requires formation of a polycrystalline silicon layer, thus resulting in an increase in the size of an element isolation region where no elements are fabricated. Therefore, the second gettering technique represents a considerable obstacle against miniaturization of an LSI circuit.
In order to solve the problems, Japanese Patent Application Laid-Open No. Hei-5-82525 describes a technique of fragmentarily forming a insulation layer on a support substrate so as to establish electrical conduction between the silicon layer and the insulation layer such that contaminants are captured by gettering sites formed on the reverse surface of the support substrate. However, according to this technique, the insulation layer is fragmentarily formed in a phase of manufacturing an SOI wafer, whereby an SOI wafer having predetermined gettering sites is manufactured. This in turn places considerable restrictions on freedom of design of an LSI circuit.
Further, the gettering sites are formed on the reverse surface of the support substrate and are effective for preventing contamination of the support substrate from the reverse surface thereof. However, the gettering sites are formed at positions distant from a silicon layer serving as an active layer. Thus, this technique also involves difficulty in attaining a sufficient effect of preventing contamination of semiconductor elements fabricated on the silicon layer, which would otherwise be caused by contaminants.